1. Field of the Invention
This invention relates to a method for the application of a gating signal in an insulated double gate field effect transistor (FET).
2. Description of the Prior Art
For the purpose of materializing an insulated gate FET having a minute channel length, the prevention of the so-called short channel effect (sudden fall of threshold voltage occurring when the channel length is shortened) is an indispensable condition.
As one of the element configurations directed toward this prevention, an insulated double gate FET illustrated in FIG. 1 may be adduced, for example (Japanese Patent No. 2021931). In the diagram, 1 denotes a substrate, 2 a second gate insulating film concurrently serving as an insulating layer for separating a semiconductor crystal layer formed on the substrate from the substrate, though not wholly illustrated, 3, 4 and 5 respectively a source region, a drain region and a channel region formed in part of the semiconductor crystal layer, 6 a first gate insulating film, 7 an insulating film, 8 a source electrode, 9 a drain electrode, 10 a first gate electrode, and 11 a second gate electrode.
This configuration, as a means to suppress the short channel effect, is said to be most effective. Specifically, it is claimed to prevent the threshold voltage from a sudden fall by shielding the channel region 5 with the first gate electrode 10 and the second gate electrode 11, i.e. an upper one and a lower one in a vertical pair, thereby suppressing the influence inflicted by the drain electric field on the potential distribution in the interface between the source and channel regions and consequently shortening the channel length and enabling the potential distribution in the interface between the source and channel regions to be stably controlled solely by the gate electrode.
How the threshold voltage is controlled constitutes an important point, namely the problem that confronts the element of this sort. Though this control is generally executed by controlling the concentration of the impurity in the channel region, the concentration of this impurity that is completely managed by the control has its upper limit set at a level in the neighborhood of 1018 cm−3 owing to the restriction to the breakdown of the semiconductor itself. When the element is minutely diminished in this case, the number of the impurity atoms within the channel region decreases so extremely that the statistic change in the number of impurity atoms between individual elements comes to manifest itself conspicuously as the change in the threshold voltage. This point brings up the problem of decline in yield to an integrated circuit that uses an extremely large number of elements.
The insulated double gate FET can avoid this problem because it is capable of using a channel region of an extremely low concentration approximating an intrinsic semiconductor without impairing the restriction of the short channel effect. For the purpose of realizing a right threshold voltage, it is inevitable to use a metal possessing an appropriate work function as the material for the gate electrode. The metal, however, allows no fine control of the work function because the work function has a discrete value for metal to metal. A method that attempts to produce a material manifesting a proper work function by using SiGe, for example, and properly selecting the ratio of Si and Ge has been proposed. This method, however, is at a disadvantage in complicating the process to be used for the production.
The preceding description has depicted the insulated double gate FET as having the two gates thereof electrically connected to each other. There has been known a method which comprises using one of the gate electrodes for signal input and applying to the other gate electrode a stated constant potential (though the magnitude of the constant potential varies at any time, there are times when the potential may be retained at least at a fixed magnitude during a period amply longer than the cycle of input signal) as illustrated in FIG. 2(d), thereby controlling the threshold voltage seen from the signal input gate at the optimum magnitude. Since the electric current flows only through the channel on the signal input gate side, this method is at a disadvantage in suffering the amount of electric current to be roughly halved from the amount obtained when the two gate electrodes are electrically connected and inducing a degradation of the load driving ability during the operation of transient response. It is further at a disadvantage in widening the so-called gate swing (otherwise called “S factor” and reported in the denomination of “mV/digit”) so much as to pose an awful question as to how much change in gate voltage is necessary for shifting the drain current by one order of magnitude below the threshold voltage. Incidentally, when the two gate electrodes are electrically connected, such a small magnitude at room temperature as about 60 mV/decade that substantially approximates the theoretical limit is realized.
This invention is directed toward providing a method for applying a gating signal in an insulated double gate FET that eliminates the drawbacks mentioned above and enables the threshold voltage to be arbitrarily controlled with high accuracy.